1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to pump circuits used in integrated circuits.
2. Description of the Related Art
In some integrated circuits, it is desirable to have a circuit that provides a high negative voltage. This is particularly true for integrated circuits that include memory devices, such as, for example, electrically erasable programmable read-only-memory (EEPROM) devices. The high negative voltage is applied to control gates of memory cells during erasure to erase the data stored in the memory cells.
An example of a pump circuit that provides a negative voltage is described in U.S. Pat. No. 5,973,979. Some N-channel negative charge pumps, such as that of U.S. Pat. No. 5,973,979, suffer from several disadvantages. First, in order to minimize the body-effect coefficient, these N-channel negative charge pumps use separate P-wells for different stages of the charge pump. The use of separate (and therefore multiple) P-wells increases the area of the charge pump circuit. Second, these negative charge pump circuits use a four phase clock for controlling the relevant gates of transistors in the charge pump circuit. Thus, they use a timing circuit of greater complexity than would be needed in a system whose clock has fewer phases. Third, these charge pump circuits include only one path for transferring charge from one stage to the next stage. As a consequence, they allow for only one charge transfer from one stage to the adjacent stage during a clock cycle.
As a result, there has been a need for charge pump circuit that addresses the shortcomings of existing charge pump circuits.
The present invention encompasses a charge pump circuit. In one embodiment, the charge pump circuit of the present invention includes: a first pumping stage, where the first pumping stage receives a first input voltage and a second input voltage and outputs a first output voltage and a second output voltage, and at least a second pumping stage coupled to the first pumping stage, where the second pumping stage receives the first output voltage and the second output voltage and outputs at least a third output voltage, further where the first output voltage and the second output voltage are output within one clock cycle.
In one embodiment, the first pumping stage receives the first input voltage and the second input voltage at a first path input of a first path and a second path input of a second path, respectively, where the first path and the second path include a first switch and a second switch, respectively, where the first switch is cross coupled to the second switch. In one embodiment, charge of one polarity is transferred to the second pumping stage via both the first and second paths in one clock cycle. In one embodiment, the first and second input voltages are clock signals whose period is equal to one clock cycle. In one embodiment, the first and second switches in each pumping stage are N-channel transistors and the N-channel transistors in each of the pumping stages of the charge pump circuit are biased by the output of the charge pump circuit.